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1

Layout Dependent Matching Analysis of CMOS Circuits

Kenichi OKADA, Hidetoshi ONODERA, Keikichi TAMARU

Journal:

Analog Integrated Circuits and Signal Processing

Year:

2000

Language:

english

File:

PDF, 141 KB

english, 2000

2

A method for improving reusability of design procedures of analog circuits—storage and reuse of design constraints and uncertain parameters

Takashi Morie, Hidetoshi Onodera, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

2000

Language:

english

File:

PDF, 217 KB

english, 2000

3

A memory efficient array architecture for real-time motion estimation

Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru

Journal:

Systems and Computers in Japan

Year:

1998

Language:

english

File:

PDF, 925 KB

english, 1998

4

MOSFET statistical modeling method using an intermediate model

Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

2001

Language:

english

File:

PDF, 312 KB

english, 2001

5

A method of extracting mosfet parameters with small model dependency using a common intermediate model

Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1996

Language:

english

File:

PDF, 892 KB

english, 1996

6

High speed merged array multiplication

Farhad Fuad Islam, Keikichi Tamaru

Journal:

Journal of Signal Processing Systems

Year:

1995

Language:

english

File:

PDF, 955 KB

english, 1995

7

Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPP

Keikichi Tamaru, Kazutoshi Kobayashi, Hidetoshi Onodera

Journal:

Computers & Electrical Engineering

Year:

1998

Language:

english

File:

PDF, 2.76 MB

english, 1998

8

A cyclic switched capacitor A–D, D–A converter

Hidetoshi Onodera, Tetsuo Tateishi, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1987

Language:

english

File:

PDF, 641 KB

english, 1987

9

A block placement procedure using a force model

Hidetoshi Onodera, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1989

Language:

english

File:

PDF, 796 KB

english, 1989

10

System design of the figure operation hardware engine used for LSI layout design rule checking

Mamoru Sakamoto, Hidetoshi Onodera, Keikichi Tamaru, Toshihiro Nomura

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1989

Language:

english

File:

PDF, 777 KB

english, 1989

11

A layout design methodology using data description with correspondence between circuit and layout

Ryosuke Okuda, Hidetoshi Onodera, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1989

Language:

english

File:

PDF, 601 KB

english, 1989

12

Shiftcompaction—quasi-two-dimensional compaction method for symbolic layout

Mamoru Sakamoto, Hidetoshi Onodera, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1990

Language:

english

File:

PDF, 946 KB

english, 1990

13

Functional information extraction from combinational circuits

Masahiko Ohmura, Hiroto Yasuura, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1991

Language:

english

File:

PDF, 811 KB

english, 1991

14

Branch-and-bound placement for building block layout

Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1993

Language:

english

File:

PDF, 932 KB

english, 1993

15

Behavioral verification of cpus using functional information extraction

Masahiko Ohmura, Keikichi Tamaru, Hiroto Yasuura

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1994

Language:

english

File:

PDF, 743 KB

english, 1994

16

A method for analog circuit design that stores and reuses design procedures

Takashi Morie, Hidetoshi Onodera, Keikichi Tamaru

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1994

Language:

english

File:

PDF, 818 KB

english, 1994

17

System design of a special-purpose computer for LSI design rule checking

Keikichi Tamaru, Hidetoshi Onodera

Journal:

Systems and Computers in Japan

Year:

1987

Language:

english

File:

PDF, 829 KB

english, 1987

18

[ACM Press the 1998 IEEE/ACM international conference - San Jose, California, United States (1998.11.08-1998.11.12)] Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98 - Proposal of a timing model for CMOS logic gates driving a CRC π load

Hirata, Akio, Onodera, Hidetoshi, Tamaru, Keikichi

Year:

1998

Language:

english

File:

PDF, 668 KB

english, 1998

19

[ACM Press the 36th ACM/IEEE conference - New Orleans, Louisiana, United States (1999.06.21-1999.06.25)] Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99 - A practical gate resizing technique considering glitch reduction for low power design

Hashimoto, Masanori, Onodera, Hidetoshi, Tamaru, Keikichi

Year:

1999

Language:

english

File:

PDF, 268 KB

english, 1999

20

[ACM Press the 28th conference - San Francisco, California, United States (1991.06.17-1991.06.22)] Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91 - Branch-and-bound placement for building block layout

Onodera, Hidetoshi, Taniguchi, Yo, Tamaru, Keikichi

Year:

1991

Language:

english

File:

PDF, 774 KB

english, 1991

21

Low Activation Energy by Polarization in a Floating Gate Structure

Nozawa, Hiroshi, Tamaru, Keikichi

Journal:

Japanese Journal of Applied Physics

Year:

1993

Language:

english

File:

PDF, 244 KB

english, 1993

22

[ACM Press the 1998 international symposium - Monterey, California, United States (1998.08.10-1998.08.12)] Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98 - A power optimization method considering glitch reduction by gate sizing

Hashimoto, Masanori, Onodera, Hidetoshi, Tamaru, Keikichi

Year:

1998

Language:

english

File:

PDF, 203 KB

english, 1998

23

[ACM Press the 2000 conference - Yokohama, Japan (2000..-..)] Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 - A method for linking process-level variability to system performances

Fujita, Tomohiro, Okada, Ken-ichi, Fujita, Hiroaki, Onodera, Hidetoshi, Tamaru, Keikichi

Year:

2000

File:

PDF, 266 KB

2000

24

“The Latest Trend of ASIC”

Tamaru, Keikichi

Journal:

IEEJ Transactions on Electronics Information and Systems

Year:

1987

File:

PDF, 373 KB

1987

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